1. Field of the Invention
The present invention relates to a semiconductor device formed on a silicon-on-insulator (SOI) structure and to a method for manufacturing the semiconductor device.
2. Description of the Related Art
As the integration density of semiconductor devices increases, the distance between devices continues to decrease. Accordingly, an isolation distance required to electrically isolate devices from each other becomes reduced considerably, and thus it is difficult to prevent transistor devices from interfering with each other through the use of conventional isolation methods, such as local oxidation of silicon (LOCOS) or trench isolation. For example, latch-up, which acts between adjacent transistor devices, occurs more frequently. In order to prevent transistor latch-up, ion implantation has been employed to prevent punch-through of an insulating layer for isolation. However, as the distance between devices decreases, ion implantation cannot be considered an effective approach to prevent latch-up.
Accordingly, a silicon-on-insulator (SOI) wafer has been developed to form devices completely isolated from each other, unlike a conventional method for forming a device directly on a silicon wafer. The SOI wafer includes a base comprised of a general silicon wafer and has a structure in which an insulator is formed on the silicon wafer and a monocrystalline silicon layer is formed on the insulator. That is, the SOI wafer has a three-layered structure including a base layer formed of silicon, an intermediate layer comprised of an insulator, and a top layer formed of monocrystalline silicon.
Devices are formed on the top layer of the SOI wafer, which is formed of monocrystalline silicon. If transistors are formed on the SOI wafer having such a structure, each of the transistors is formed in an island shape so that the transistor devices can be completely isolated from one another and punch-through or latch-up can be prevented.
However, transistors formed on a semiconductor wafer, each generally including three terminals including a gate, a source, and a drain, and a ground path, must be prepared in the semiconductor wafer so that the basic circuit structure of a transistor device can be completed. However, in the case of the SOI wafer, an insulator is formed under the monocrystalline silicon layer of the SOI wafer, and thus it is difficult to provide a stable ground path perforating the insulator in the SOI wafer. Therefore, electric charges generated when an external voltage is applied to devices having an island shape cannot be released. Thus, the reference voltage of a transistor becomes unstable, and the operational characteristics of a device deteriorate.
To solve the above-described problems, it is an object of the present invention to provide a semiconductor device on a SOI wafer which is capable of stably maintaining the electrical characteristics of a device, such as threshold voltage.
In accordance with the invention, there is provided a semiconductor device on a silicon-on-insulator (SOI). The device includes a semiconductor wafer having a SOI structure and including an insulating layer having a predetermined thickness and a monocrystalline silicon layer formed on the insulating layer. An isolation insulating layer is formed on the insulating layer on the semiconductor wafer. A gate comprised of a gate dielectric layer and a gate conductive layer are sequentially stacked on the monocrystalline silicon layer. Insulating layer spacers are formed at the sidewalls of the gate, and a source junction and a drain junction are asymmetrically formed at either side of the gate between the isolation insulating layer spacers and the insulating layer.
In one embodiment, the isolation insulating layer includes a silicon oxide layer. The isolation insulating layer can be a silicon oxide layer formed to fill a trench on the semiconductor wafer.
The gate conductive layer may be formed to include a silicide layer formed by allowing titanium, cobalt, or molybdenum with silicon in order to deposit impurity-doped polysilicon or increase the conductivity of the gate conductive layer.
The gate dielectric layer, which is interposed between the gate conductive layer and the monocrystalline silicon layer and controls the threshold voltage of a MOS transistor, may be a thin silicon oxide layer.
The insulating layer spacers are preferably formed of a silicon nitride layer by chemical mechanical deposition (CVD).
The semiconductor device according to the first embodiment of the present invention may further include a channel junction formed at the surface of the monocrystalline layer at either side of the gate, and thus a short channel effect can be prevented from occurring at the semiconductor device.
The drain junction may further include a reinforced drain junction formed under the drain junction.
In accordance with the invention, there is also provided a semiconductor device on a SOI, including a semiconductor wafer having a SOI structure and including an insulating layer having a predetermined thickness and a monocrystalline silicon layer formed on the insulating layer, an isolation insulating layer formed in the monocrystalline silicon layer, a gate comprised of a gate dielectric layer and a gate conductive layer, which are sequentially stacked on the monocrystalline silicon layer, first insulating layer spacers formed at the sidewalls of the gate, second insulating layer spacers formed at the sidewalls of the first insulating layer spacers, a source junction and a drain junction formed at either side of the gate between the first insulating layer spacers and the isolation insulating layer, and a reinforced drain junction formed between the second insulating layer spacers and the isolation insulating layer to extend from the lower portion of drain junction.
Here, the isolation insulating layer includes a silicon oxide layer. The isolation insulating layer is preferably formed by depositing a silicon oxide layer to fill a trench on the semiconductor wafer.
Preferably, the gate conductive layer includes a conductive polysilicon layer formed by doping polysilicon with impurities or a silicide layer formed by allowing silicon react with a metal.
In one embodiment, the gate dielectric layer, which is interposed between the gate conductive layer and the monocrystalline silicon layer and controls the electrical characteristics of a transistor including threshold voltage, is formed of a thin silicon oxide layer. However, in the case of using a thin silicon oxide layer as the gate dielectric layer, the reliability of a semiconductor device may deteriorate. Thus, the gate dielectric layer is preferably formed of a silicon oxynitride (SiON) layer.
The first insulating layer spacers may be formed of a silicon nitride layer or a silicon oxide layer, and the second insulating layer spacers may be formed of a silicon oxide layer or a silicon nitride layer. However, in the case of forming a gate of a silicide layer, the first and second insulating layer spacers are preferably formed of a silicon nitride layer because an oxide layer can be easily etched by an etchant for removing a metal used to form the silicide layer.
The semiconductor device according to the second embodiment of the present invention may further include a channel junction formed at the surface of the monocrystalline layer at either side of the gate, and thus a short channel effect can be prevented from occurring at the semiconductor device.
As described above, in the method for manufacturing a semiconductor device on a SOI wafer according to the present invention, a source and a drain are asymmetrically formed. Thus, a stable ground in a transistor can be achieved, and a semiconductor device which is capable of stably maintaining threshold voltage can be made.